It added simplified AXI connections between SystemVerilog instances and provided automatic wrapper creation for all AMD IP and Block Designs.
The release included multi-threaded support for faster device image generation and reduced physical optimization (PhysOpt) compile times. The "Fixed" Versions: 2020.2.1 and 2020.2.2 xilinx vivado 20202 fixed
This update primarily added support for new device packages in the Kintex and Virtex UltraScale+ families, such as the XCKU095_CIV and XCVU190_CIV . The 2020
The 2020.2 cycle addressed several legacy issues from the 2020.1 release: Downloads - AMD xilinx vivado 20202 fixed
If you are experiencing bugs in the base 2020.2 build (SW Build 3064766), Xilinx released specific tool updates to "fix" known issues:
Even in 2020.2.2, some users encountered the [DRC RTSTAT-6] error regarding partial route conflicts, which was documented in Xilinx Answer 76156 . Common Bug Fixes and Resolved Issues